1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device including field effect transistors.
2. Description of the Background Art
Recently, there has been an increasing demand for a semiconductor device, in particular a Dynamic Random Access Memory (DRAM), which can operate at higher speed. To accomplish such a fast-operating DRAM, it is essential to improve the performance including the operational speed, for example, of a field effect transistor (FET) located in the peripheral circuit region of the DRAM performing data transmission and the like. Effective ways to improve such performance of the FET include: making its gate insulating film thinner, reducing the threshold voltage, and shortening the gate length.
For making a thinner gate insulating film as described above, which directly contributes to the improvement of performance of the FET, attempts have been made to obtain a gate insulating film with a thickness of 3 to 4 nm. However, in the same DRAM, there exists another FET to which a high voltage is to be applied. In particular, a relatively high voltage is applied to an FET in a memory cell region. If a gate insulating film of such FET is made thinner as stated above, there may arise problems such as an increased leakage current and a decreased breakdown voltage.
Therefore, the film thickness of a gate insulating film of the FET in the memory cell region to which a relatively high voltage is to be applied cannot be made thinner as that in the peripheral circuit region. It is thus needed to form gate insulating films of different film thicknesses on a single semiconductor substrate.
By reducing the threshold voltage, which is already mentioned above as another approach to the improved performance of an FET, a large ON-state current can be obtained in the FET even with a low voltage. On the other hand, however, due to such reduction in the threshold voltage, the leakage current will abruptly increase when the FET is turned off. As a result, power consumption of the DRAM will increase.
Accordingly, there has been generally employed a method in which an FET having a first, low threshold voltage and another FET having a second threshold voltage 0.2 to 0.4V higher than the first one are formed, so that the leakage current generated at an FET having the first, low threshold voltage is cut off employing an FET having the second, relatively higher threshold voltage.
Thus, in the peripheral circuit region of the DRAM, it is required to form a plurality of FETs having different threshold voltages. Herein, the threshold voltages of the FETs are generally adjusted by introducing impurities into a semiconductor substrate.
As described above, in a DRAM, or a semiconductor device for which a high-speed operation is highly demanded, it is necessary to form, on a single semiconductor substrate, a plurality of FETs having gate insulating films of different film thicknesses and different threshold voltages, respectively.
For manufacturing a semiconductor device including such a plurality of FETs in which film thicknesses of the gate insulating films as well as the threshold voltages are different from one another as described above, the following manufacturing process has been employed.
Referring to FIG. 24, a field oxide film 102 and an oxide film 103 are first formed on the main surface of a semiconductor substrate 101. At this time, a first resist pattern is formed for the formation of field oxide film 102.
Next, an n type impurity is introduced into a prescribed region in semiconductor substrate 101 to form an n type well 107 and n type impurity regions 130a-130c. Here, a second resist pattern is formed to be used as a mask when introducing the n type impurity.
A p type impurity is then introduced into a prescribed region of the main surface of semiconductor substrate 101 to form a p type well 110 and p type impurity regions 131a-131c. Here, a third resist pattern is formed to be used as a mask when introducing the p type impurity.
Thereafter, the p type impurity is additionally introduced into the main surface of semiconductor substrate 101 located in a memory cell region for adjusting the threshold voltage of an FET therein. Accordingly, a p type impurity region 127 of high concentration is formed. At this time, a fourth resist pattern is formed and used as a mask when additionally introducing the p type impurity.
Still referring to FIG. 24, for adjusting the threshold voltage of an FET in the peripheral circuit region, a p type impurity 113 is introduced into semiconductor substrate 101, and thus a second p type impurity region 114 of high concentration is formed. For using as a mask when the p type impurity 113 is introduced, a fifth resist pattern 104 is formed.
In this way, impurity concentration at respective regions in semiconductor substrate 101 is adjusted so as to adjust the threshold voltages of respective FETs.
Thereafter, a plurality of FETs including gate insulating films of different film thicknesses are formed in prescribed regions of semiconductor substrate 101. Specifically, following the steps as described above, oxide film 103 is first removed from the main surface of semiconductor substrate 101.
Next, with reference to FIG. 25, on the main surface of semiconductor substrate 101, an oxide film 111 is formed, which is to be a gate insulating film having a first film thickness. A polycrystalline silicon (polysilicon) film 112 is formed on oxide film 111.
Thereafter, a sixth resist pattern (not shown) is formed on polysilicon film 112. Using this resist pattern as a mask, oxide film 111 and polysilicon film 112 are etched away in regions A and B. The resist pattern is then removed. As a result, the structure shown in FIG. 25 is obtained.
Thereafter, on the main surface of semiconductor substrate 101 in regions A and B as well as on polysilicon film 112, an oxide film (not shown) is formed to be a gate insulating film having a second film thickness. A second polysilicon film (not shown) is also formed on this oxide film.
Next, in regions A and B, a seventh resist pattern is formed on the second polysilicon film. Using this resist pattern as a mask, the second polysilicon film and the oxide film located in regions other than the regions A and B are etched away. The resist pattern is then removed.
Next, after depositing a conductive film over the entire surface, an eighth resist pattern is formed and is used as a mask for etching to form a gate insulating film and a gate electrode.
An impurity is then introduced into semiconductor substrate 101 to form source/drain regions of each FET.
There has thus been formed a semiconductor device including a plurality of FETs having gate insulating films of different film thicknesses and different threshold voltages.
In the manufacturing process as described above, the formation and removal of resist patterns need to be repeated eight times before completing the formation of gate electrodes and gate insulating films, and therefore, the number of manufacturing steps is substantially increased in comparison with those for a conventional semiconductor device. Such increase of the number of manufacturing steps has caused increase in manufacturing cost.